Digital Processing-In-Memory

Digital PIM macro is an emerging VLSI macro that can perform Hadamard product in digital domain, besides the memory read/write function. Analog-Digital converters are saved from APIM by integrating local processing units (LPU) into the macro.

For research idea introduction visit [B. Yan, et al. ISSCC'22]

Mode/Function

• Write : put a piece of data into the memory
• Read : fetch data from the memory (given the data is already written into the memory)
• CIM : compute-in-memory mode, in the following example, CIM mode perform:

• In $dat{a}_{i,j}$, $i\in N$ and $j\in N$ are selected from the bulk of the data bitcell matrix by designated address
• m could be 1, 2, 3, ... The example code only shows the case of m=1

Address Map

An example of DPIM:

IO Port

macro global ports:

• port: clock
  • input
  • in example code: 1bit
  • macro clock
• port: en or cs
  • input
  • in example code: 1bit
  • global enable memory mode ports:
• port: addr
  • input
  • in example code: 12bit
  • controlling address
• port: d
  • input
  • in example code: 32bit
  • input data port
• port: q
  • output
  • in example code: 32bit
  • output data port
• port: we
  • input
  • in example code: 1bit
  • write enable, high active

CIM mode ports:

• port: cme
  • input
  • in example code: 1bit
  • CIM mode enable, high active
• port: cmIn or cim_in
  • input
  • in example code: 4bit for each entry; it is a 4-element vector
  • CIM mode input operands
• port: cmIn or cim_out
  • output
  • in example code: 6bit for each entry (determined by the ADC precision); it is a 8-element vector
  • CIM mode input operands

Timing Diagram

Note: A0, A1, ... are addresses; D0, D1, ... are data.

Core Code in Verilog

//--------------Internal variables---------------- 
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
//--------------Code Starts Here------------------ 
// Memory Write Block 
// Write Operation : When we = 1, cs = 1
always @ (posedge clk)
begin : MEM_WRITE
   if ( cs && !web ) begin
       mem[a] = d;
   end
end

// Memory Read Block 
// Read Operation : When we = 0, oe = 1, cs = 1
always @ (posedge clk)
begin : MEM_READ
  if (cs && web) begin
    if(cimeb) begin
      q = mem[a];
    end else begin
      // enter CIM mode, this is only behavioral sim
      // actual CIM macro is designed with transistor-level circuits
      cim_out = LPU_Func(cim_in, mem)
    end
  end
end